Productive parallel programming for FPGA with high-level synthesis

Your are hereby cordially invited to a tutorial on:

“Productive parallel programming for FPGA with high-level synthesis“

Location: ETH Zurich, ML H 37.1
Speakers: Johannes de Fine Licht and Torsten Hoefler

Time: 14:00 – 17:30, Tuesday May 15, 2018

As the scale of large high performance computing systems increases, so does their power consumption, making energy efficiency a first class citizen in their design. While GPUs and custom processors have improved this situation significantly, reconfigurable architectures, such as FPGAs, promise another major step in energy efficiency, constituting a

 middle ground between fixed hardware architectures and custom-built ASICs.

Programming FPGAs has traditionally been done in hardware description languages, requiring extensive hardware knowledge and significant engineering effort. This tutorial shows how high-level synthesis (HLS) can be harnessed to productively achieve scalable pipeline parallelism on FPGAs.  Attendees will learn how to target FPGA resources from high-level C++ or OpenCL code, guiding the mapping from imperative code to hardware, enabling them to develop massively parallel designs with real performance benefits. We treat concrete examples well known from the software world, relating traditional code optimizations to both corresponding and new transformations for hardware, building on existing knowledge when introducing new topics.  By bridging the gap between software and hardware optimization, our tutorial aims to enable developers from a larger set of backgrounds to start tapping into the potential of FPGAs with real high performance codes.

If you wish to attend, please register by May 8 in the following form:

The tutorial is limited to 50 participants, on a first come, first served basis.

This event will take place at ETH Zurich May 15, 14:00-17:30 in ML H 37.1.

The speakers will be Johannes de Fine Licht and Prof. Torsten Hoefler, from the Scalable Parallel Computing Lab/Systems Group at ETH Zurich.

Our tutorial will be HPC-centric, approaching FPGAs and high-level synthesis (HLS) from a performance engineering point of view.

We will cover all important FPGA-specific optimizations that you need to achieve a scalable hardware implementation by applying them to concrete examples.

The presentation will be interleaved with live demos, exposing attendees to real code synthesized with a real HLS tool.

The demos will use Xilinx’ Vivado HLS, but all optimizations performed are platform agnostic.

We additionally cover the (relatively minor) differences between Vivado HLS and Intel’s OpenCL for FPGAs.

 – Proficiency in C++

 – Basics of FPGA architecture

 – Performance optimization techniques on CPU/GPU (tiling, unrolling,

    vectorization)

The material covered in the demos will be handed out to attendees prior to the tutorial, in additional to a virtual machine with the tools necessary to run the examples.

More information on the tutorial available at: https://spcl.inf.ethz.ch/Teaching/2018-hls/