Courses and Workshops SPEEDUP

42nd SPEEDUP Workshop on Adaptive Mesh Refinement (AMR), Aug 29/30 2013, PSI

You are invited to participate to the

42nd SPEEDUP Workshop on High-Performance Computing
with focus on Adaptive Mesh Refinement (AMR)
+ Tutorial on the Intel Xeon Phi
Paul Scherrer Institut, Villigen, Switzerland
August 29 – 30, 2013

The intention of this workshop is to present and discuss the state-of-the-art in high-performance and parallel scientific computing. Presentations will focus on algorithms, applications, and software issues related to high-performance parallel computing. The focus of the workshop on Thursday Aug 29 will be on Adaptive Mesh Refinement (AMR). Adaptivity in general hampers load-balance. The scientific program of Aug 29 consists of six 45-minute talks and a poster session. Please encourage your collaborators to upload an abstract. The deadline is Aug 18, 2013. On August 30 we will organize a tutorial on the Intel Xeon Phi (also known as Intel MIC. It will be taught by people from Intel.

Workshop’s home page »

Directions

The conference will take place at the Paul Scherrer Institut, PSI West, in the Auditorium WHGA/001. The tutorial will take place at PSI East OSGA-OG08 (watch the signs).

Program

Thursday August 29

8:45 – 9:30 Registration
9:30 – 9:35 Welcome Opening (Andreas Adelmann – PSI)
9:35 – 10:20 Parallel adaptive mesh refinement using multiple octrees and the p4est software, Carsten Burstedde (U of Bonn)
10:20 – 10:55 BoxLib: A Software Framework for Block-Structured AMR Applications, Ann Almgren (Lawrence Berkeley NL)
10:55 – 11:20 Coffee break
11:20 – 12:05 Block structured AMR in astrophysics (tentative), Francesco Miniati (ETH Zurich)
12:05 – 12:50 ASPECT: An advanced mantle convection solver based modern numerical software, Martin Kronbichler (TU Munich)
12:50 – 14:15 Lunch break
14:15 – 15:00 A lightweight approach to parallel adaptivity – design, implementation, and application in cardiac electrophysiology, Rolf Krause (USI Lugano)
15:00 – 15:45 The Intel Xeon Phi (a.k.a. Intel MIC) (tentative), Marie-Christine Sawley (Intel Exascale Lab)
15:45 – 17:00 Coffee/Apero + poster session
17:00 – 17:30 General Assembly of the Speedup Society

Friday August 30

Tutorial on the Intel Xeon Phi by Herbert Cornelius

08.30 – 09.30 General overview
09.30 – 10.00 Coffee break
10.00 – 11.00 Programming environment
11.00 – 12.00 MPI
12.00 – 13.00 Lunch break
13.00 – 15.00 Optimisation, performance analysis and MKL
15.00 – 15.30 Coffee break
15.30 – 17.00 Hands on Session

Fees

  • Workshop: CHF 50 (free for bachelor and master students)
  • Tutorial: CHF 150 (CHF 50 for bachelor and master students)

Details and the registration form can be found here.

Organizing committee

P. Arbenz (ETH Zurich), H. Burkhart (U of Basel), R. Krause (USI Lugano), O. Schenk (USI Lugano), S. Deparis (EPF Lausanne), V. Rezzonico (EPF Lausanne), A. Janka (EIA Fribourg), A. Adelmann (PSI Villigen), D. Obrist (ETH Zurich), H. Nordborg (HSR).